Acomputer program for automatically extracting from transistor-level netlist to a gate-level netlist.
Refer to the graph above,
- Input of FROSTY
FROSTY reads in a transistor level static CMOS netlist (object circuit), and a library file in the SPICE format. The library file contains user specified subcircuit blocks that are to be recognized from the object circuit, for example, D-flip-flop, Latch, Adder, and so on.
- Two-Phase Extraction Process
FROSTY works in two phases. In Phase I, FROSTY automatically extracts all the standard CMOS gates, such as inverter, nand and nor gates. In Phase II, FROSTY extractes all the subcircuit blocks defined in the library.
- Output of FROSTY
FROSTY outputs two files. One is a Verilog format gate-level netlist. Another is a header file, it contains the functional definitions of all used standard CMOS gates. Together with Verilog model descriptions of the library blocks, the extracted gate-level netlist and the header file can be simulated in any digital simulator.