Abstraction of digital MOS circuits as switch-level networks has proven very useful for VLSI automation. Symbolic analysis of switch- level networks by representing the signal at the gate of a MOS transistor as a Boolean variable has been shown to be efficient for verification in terms of functionality and timing. For this work, in addition to expressing the signal at the gate of MOS transistors as Boolean variables, we represent the design parameters of the transistors as algebraic symbols. In this paper, we present the theory for unified symbolic analysis in terms of both algebraic and Boolean symbols. Our formulation is general and is valid for extensions of conventional switched linear networks with various circuit elements like passive elements, current sources, etc. The theory developed for mixed algebraic and Boolean symbolic analysis is applied for symbolic delay estimation in logic-stages with interconnects. Instead of conventional numeric delay estimation techniques, our method provides a single closed-form analytic delay expression that is symbolic in terms of both Boolean variables and the geometric design parameters of transistors and interconnects. Such expressions provide accurate estimations of signal delay over any input pattern and extensive variation in design variables like width and lengths of transistors and interconnects. This is implemented in a computer program and validated on modern VLSI technologies.