Introduction of IPRAIL
Device matching and symmetry, parasitics, current density in interconnects, thermal, and substrate effects are of utmost importance in high performance analog/RF circuits. The complexity involved in modeling these layout-effects for incorporation into layout-automation engines is immense. Thus, traditionally, analog/RF layouts have been crafted manually by expert layout-designers to squeeze-in the desired performance through intricate layout-geometries.
Over the years, several attempts on analog layout-automation are based on a two-step process of first creating device-level macro-cells and then generating the layout through the floorplanning, placement and routing coupled with optimizations. Despite the generality of these approaches, they seldom achieve circuit-performance comparable to manual layouts. The biggest drawback of the macro-cell based approaches, thus, lies in their inability to incorporate human intelligence in their automation schemes.
On the contrary, the proposed work addresses the fast and reliable automatic generation of analog/RF layouts by utilizing the intellectual properties and expertise embedded in existing layouts. This work is established on the premise that the design of new analog/RF circuits often start by renovating existing designs. The proposed method constructs a symbolic structural template from an existing analog/RF layout, and uses it to generate multiple new layouts satisfying different sets of device sizes and technology processes. A direct application of this methodology is in automatic re-targeting of analog layouts to new processes and specifications.
Figure 1: Analog layout retargeting methodology
For this method, IPRAIL (Intellectual Property Reuse-based Analog IC Layout) has been developed, where the overview methodology is shown in Figure 1. The symbolic structural template comprises of a set of constraints that govern the connectivities, floorplan, placement topology and matching/symmetry in the input layout. It is also technology independent as technology-related constraint-values are symbolic. To generate the layouts, the template is then updated with new constraint values according to the new technology process design rules and the new device sizes necessary to meet the desired specifications. Solution of these template-constraints can be viewed as a modified symbolic-compaction problem. This is accomplished by a combination of graph-based shortest path and linear-programming approaches.
The key contribution to the proposed approach lies in the preservation of intricacies embedded in existing layouts, which is the major concern un-addressed in. Although the layout-topologies are restricted, this method demonstrates an exiting potential in a reuse based design environment and is proved to achieve layouts comparable to manually crafted ones in quality and performance.
New functionalities recently added to the IPRAIL tool-suite are in the area of symmetry detection, template-reduction, passive-device retargeting and layout-dependent substrate modeling. For symmetry, HiLSD (Hierarchical Layout Symmetry Detector) has been developed and integrated to IPRAIL. HiLSD symmetry detection and constraint generation algorithms automatically identify only the designer-intended symmetries in the existing layouts. This is accomplished by a combination of netlist partitioning, subgraph isomorphism based subcircuit extraction, layout-pattern identification and subsequent geometry-comparison. Subsequently, a multi-level netlist-layout partitioning and mapping scheme are developed to intelligently identify only non-redundant and essential constraints from hierarchical layouts. Unlike various analog layout automation schemes that can handle complexity only up to operational amplifiers, the IPRAIL tool-suite has successfully retargeted the analog section of 5-bit ADC.
A challenge in retargeting RF layouts lies in the large number of vias/contacts owing to the large currents and EM effects, which leads to an unmanageable template size. An innovative via deletion and re-population method has been developed to reduce the template size. In addition, various schemes have been developed for retargeting on-chip passive devices, including inductors, by imposing special constraints in the template. Furthermore, as the extracted template is fully symbolic, it can be reused to generate multiple layouts, one for each target technology and specification combination.
For multi-GHz RF circuits, substrate-parasitics often result in significant performance degradation. Studies, supported by experiments, infer that substrate parasitics are a function of layout-patterns. Consequently, substrate models that incorporate layout effects have been developed and integrated in the IPRAIL tool-suite.
The reuse-based layout-automation scheme presented here promises to be capable of generating layouts that are comparable in quality to manual-layouts. The technique significantly reduces design cycle time. Several layout-centric effects are modeled and incorporated into the tool-suite. High quality layouts that normally take few weeks to craft manually are generated in a few minutes. Future researches are directed towards interconnect sizing/spacing for optimization of circuit performance. This entails parasitic extraction and development of new algorithms for layout optimization with non-linear constraints.