The Large Hadron Collider (LHC) is the world's largest particle physics experiment, and it is located at CERN in Geneva, Switzerland. It is a 27km long particle accelerator which takes two protons, brings them to nearly the speed of light and then collides them together inside the detectors of the different experiments stationed around its ring. In total the LHC is comprised of seven separate experiments: ALICE, LHCb, CMS, TOTEM, LHCf, MoEDAL, and ATLAS. Over the past few years the LHC has undergone upgrades it order to increase the energy of the collisons up from 7 TeV to 13 Tev.
The ATLAS experiment (A Toroidal LHC Apparatus) is a massive 7 ton general purpose particle detector investigating the largest range of physics possible. ATLAS is a 4-pi detector which means that the interaction (collision) point is fully surrounded by detector material; this is so to ensure that all possible particle flight paths are detected. Four componenets of ATLAS make this possible: the Inner Detector which is composed of several tracking detectors to track particle movement, the Calorimeters which measure the energy of the particles, the Muon Detectors that detect the Muons and neutrinos which are still able to have energy at such great distances from the interaction point, and the ATLAS trigger system which coordinates the actions and data collection of all sub-detectors.
The Inner Detector is made of three tracking layers: the Pixel Detector, the Semi-Conductor (SCT), and the Transition Radiatoin Detector (TRT). I work on the Pixel Detector, which is the innermost layer of ATLAS, and its made of 4-Layers: Layer-1, Layer-2, B-Layer, and Insertable B-Layer (IBL). Its purpose is to detect and track the particles as they come out of the collisions. It does this by using special sensors known as pixels (because its similarity with a camera) which are arranged into large arrays and then readout and controlled using front end electronics. Front-End electronics are specialized chips that are on the detector and use both digital and analog circuits to readout and calibrate the pixel arrays. This data is then readout using a DAQ chain; after the DAQ chain has readout the data it forwards it to long-term storage. The DAQ chain involves two main components: the Back-of-Crate Card (BOC) and the Readout Driver (ROD). The BOC is responsible for communication with the FE and offline storage while the ROD is responsible for taking the data from the FEs and using it, as well as information sent from ATLAS to build the physics events. Both these components rely heavily of the use of FPGAs to accomplish their goals.
The main focus ofour work is FPGA development for the datapath in the ROD. The ROD's datapath is responsible for several tasks including: FE data formatting, error checking, event building with FE data and ATLAS event information, and finally routing of the event back to the BOC. FPGAs are heavily leveraged in these systems for three reasons: low NRE cost, rapid development, and a large reconfigurable fabric to take advantage of the readout tasks need for spatial parallelism.
This work is done in collaboration with Prof. Hsu and the UW physics department. It is also done in collaboration with several other universities and institutions most notably INFN Bologna who are in charge of ROD development. This work is supported by US ATLAS and well as CERN.