A Comparison of ASIC
Implementation Alternatives

A Project Report
Submitted to the Faculty of the Department of
Electrical and Computer Engineering
Northwestern University

In Partial Fulfillment of the Requirements
for the Master of Science Degree
(Field of Electrical Engineering)


George Oliver Stone IV

October, 1996


A physical implementation of an ASIC design can be produced using one of four general technologies: full custom, standard cell, gate array, or field programmable gate array. The choice of which technology to use depends on design size, desired performance, number of units, and time to market issues. This study presents an analysis of these issues for each technology. To do this, designs were created and implemented in each technology, from which data was gathered and compared. Also, foundries were polled to obtain information on each technology. This study describes the technologies, the circuit designs used to compare them, and the results from the analysis of these issues.

Table of Contents

Chapter 1. Introduction 4

Chapter 2. Technologies 6

2.1. Full Custom 6
2.2. Standard Cell 7
2.3. Gate Array and Sea-of-Gates 9
2.4. FPGA 10

Chapter 3. Circuits 13

3.1. Combinational 13
3.2. Sequential 14
3.3. Additional Circuits 17

Chapter 4. Methodology 22

Chapter 5. Results 25

5.1. Area Results 25
5.2. Performance 27
5.3. Other Issues 29

Chapter 6. Conclusions 31

References 33

Appendix A. DNA Design Details 35

Appendix B. Verilog Code 39

Appendix C. Full Custom Implementations 49