Multi-FPGA Systems by Scott Hauck


Multi-FPGA systems are a growing area of research. They offer the potential to deliver high performance solutions to general computing tasks, especially for the prototyping of digital logic. However, to realize this potential requires a flexible, powerful hardware substrate and a complete, high quality and high performance automatic mapping system.

The primary goal of this thesis is to offer a disciplined look at the issues and requirements of multi-FPGA systems. This includes an in-depth study of some of the hardware and software issues of multi-FPGA systems, especially logic partitioning and mesh routing topologies, as well as investigations into problems that have largely been ignored, including pin assignment and architectural support for logic emulator interfaces. We also present Springbok, a novel rapid-prototyping system for board-level designs.

About the On-line Versions of the Thesis

Two postscript versions of this thesis are available here. One contains the complete thesis, and is the best choice for people who wish to print out the whole thesis. A second version is broken into smaller sections, and is easier to browse online when the user is only interested in certain sections. The individual sections, taken as a whole, contain the entire thesis. Thus, one could just take all the sections individually. However, the size of all the individual sections combined is much larger due to font inclusion and other overheads.

Note that this thesis is intended to be printed double-sided. Thus, margins and page numbers are adjusted, and blank pages inserted, to aid in the layout.

There is also a complete version of the thesis in PDF, Adobe Acrobat's portable document format.

Anon FTP of the Thesis

A compressed version of the complete thesis is available via anonymous ftp. To access it, ftp to as anonymous. The file is pub/hauck/ . Since it is compressed, be sure to set binary mode.

Complete Postscript Thesis (256 pages, 5.3 MB)

Complete PDF Thesis (256 pages, 1.3 MB)

Thesis Pieces

o Title Pages (6 pages, 1.4 MB)
o Abstract (2 pages, 1.3 MB)
o Tables of Contents, Acknowledgements, Dedication (14 pages, 1.4 MB)
o Chapter 1. General Introduction (5 pages, 1.4 MB)
o Chapter 2. Circuit Implementation Alternatives and Technologies (37 pages, 3.1 MB)
o Chapter 3. Multi-FPGA System Applications (6 pages, 1.4 MB)
o Chapter 4. Logic Validation (9 pages, 1.4 MB)
o Chapter 5. Multi-FPGA System Hardware (14 pages, 1.9 MB)
o Chapter 6. Springbok (11 pages, 1.6 MB)
o Chapter 7. Mesh Routing Topologies (17 pages, 1.6 MB)
o Chapter 8. Logic Emulator Interfaces (12 pages, 1.4 MB)
o Chapter 9. Multi-FPGA System Software (19 pages, 1.5 MB)
o Chapter 10. Bipartitioning (38 pages, 1.6 MB)
o Chapter 11. Logic Partition Orderings (19 pages, 1.5 MB)
o Chapter 12. Pin Assignment (22 pages, 1.6 MB)
o Chapter 13. Conclusions and Future Work (8 pages, 1.4 MB)
o References (13 pages, 1.4 MB)
o Curriculum Vitae (4 pages, 1.4 MB)

For access to the rest of my work, and related papers, please see my homepage.